Method for producing an array of thin-film photovoltaic cells having an etchant-resistant electrode and an integrated bypass diode associated with a plurality of cells and a panel incorporating the same

ABSTRACT

An array of series-connected solar cells is formed on a support layer with at least a two cells being adjacent and a third solar cell being either adjacent or separated from the second solar cell. A portion of the photovoltaic junction layer is separated from the first solar cell. The semiconducting material of the first type of the separated portion is electrically connected with the semiconducting material of the second type of the second solar cell through physical contact between the front electrode of the first cell and the back electrode of the second cell. The material of the second type of the separated portion of the junction layer is connected with the semiconducting material of the first type of the third cell to define a bypass diode that is in parallel and in opposition to the second and the third solar cells.

CLAIM OF PRIORITY

This application claims priority from each of the following UnitedStates Provisional Applications, each of which is hereby incorporated byreference:

-   (1) Method For Producing A Thin-Film Photovoltaic Cell Having An    Etchant-Resistant Electrode And An Integrated Bypass Diode And A    Panel Incorporating The Same, Application Ser. No. 61/414,464, filed    Nov. 17, 2010 (CL4618);-   (2) A Thin-Film Photovoltaic Cell Having An Etchant-Resistant    Electrode And An Integrated Bypass Diode And A Panel Incorporating    The Same, Application Ser. No. 61/414,467, filed Nov. 17, 2010    (CL5112);-   (3) Method For Producing An Array Of Thin-Film Photovoltaic Cells    Having An Etchant-Resistant Electrode And An Integrated Bypass Diode    Associated With A Plurality Of Cells And A Panel Incorporating The    Same, Application Ser. No. 61/414,479, filed Nov. 17, 2010 (CL5230);-   (4) Array Of Thin-Film Photovoltaic Cells Having An    Etchant-Resistant Electrode And An Integrated Bypass Diode    Associated With A Plurality Of Cells And A Panel Incorporating The    Same, Application Ser. No. 61/414,486, filed Nov. 17, 2010 (CL5231);-   (5) Method For Producing An Array Of Thin-Film Photovoltaic Cells    Having A Totally Separated Integrated Bypass Diode And Method For    Producing A Panel Incorporating The Same, Application Ser. No.    61/485,695, filed May 13, 2011 (CL5113);-   (6) Array Of Thin-Film Photovoltaic Cells Having A Totally Separated    Integrated Bypass Diode And A Panel Incorporating The Same,    Application Ser. No. 61/485,740, filed May 13, 2011 (CL5114);-   (7) Method For Producing An Array Of Thin-Film Photovoltaic Cells    Having A Totally Separated Integrated Bypass Diode Associated With A    Plurality Of Cells And Method For Producing A Panel Incorporating    The Same, Application Ser. No. 61/485,745, filed May 13, 2011    (CL5232); and-   (8) Array Of Thin-Film Photovoltaic Cells Having A Totally Separated    Integrated Bypass Diode Associated With A Plurality Of Cells And A    Panel Incorporating The Same, Application Ser. No. 61/485,751, filed    May 13, 2011 (CL5233).

CROSS-REFERENCE TO RELATED APPLICATIONS

Subject matter disclosed herein is disclosed in the following copendingapplications, all filed contemporaneously herewith and all assigned tothe assignee of the present invention:

-   Method For Producing A Thin-Film Photovoltaic Cell Having An    Etchant-Resistant Electrode And An Integrated Bypass Diode And A    Panel Incorporating The Same, application Ser. No. ______, filed    Nov. 17, 2010 (CL4618);-   A Thin-Film Photovoltaic Cell Having An Etchant-Resistant Electrode    And An Integrated Bypass Diode And A Panel Incorporating The Same,    application Ser. No. ______, filed Nov. 17, 2010 (CL5112);-   Array Of Thin-Film Photovoltaic Cells Having An Etchant-Resistant    Electrode And An Integrated Bypass Diode Associated With A Plurality    Of Cells And A Panel Incorporating The Same, application Ser. No.    ______, filed Nov. 17, 2010 (CL5231);-   Method For Producing An Array Of Thin-Film Photovoltaic Cells Having    A Totally Separated Integrated Bypass Diode And Method For Producing    A Panel Incorporating The Same, application Ser. No. ______, filed    May 13, 2011 (CL5113);-   Array Of Thin-Film Photovoltaic Cells Having A Totally Separated    Integrated Bypass Diode And A Panel Incorporating The Same,    application Ser. No. ______, filed May 13, 2011 (CL5114);-   Method For Producing An Array Of Thin-Film Photovoltaic Cells Having    A Totally Separated Integrated Bypass Diode Associated With A    Plurality Of Cells And Method For Producing A Panel Incorporating    The Same, application Ser. No. ______, filed May 13, 2011 (CL5232);    and-   Array Of Thin-Film Photovoltaic Cells Having A Totally Separated    Integrated Bypass Diode Associated With A Plurality Of Cells And A    Panel Incorporating The Same, application Ser. No. ______, filed May    13, 2011 (CL5233).

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a method for producing a thin-filmphotovoltaic cell having a cell level integrated bypass diode and to thephotovoltaic cell produced thereby; and, in particular, to a methodwhich employs one or more chemical etchant(s) to separate a portion of aphotovoltaic cell and, by appropriate electrical interconnection, toutilize the separated portion to define a bypass diode for a cell.

2. Description of the Art

A photovoltaic cell converts solar radiant energy (sunlight) incidentthereon into electrical energy as the result of the photovoltaic effect.Of particular recent interest is the large-scale and cost-effectiveconversion of solar radiation into electricity using arrays ofphotovoltaic cells assembled into photovoltaic panels.

A typical first generation photovoltaic panel involves first producing alarge number of photovoltaic cells from thinly sliced substrates ofsingle or polycrystalline silicon. Cells approximately fifteencentimeters square (15 cm×15 cm) are cut from silicon wafers a fewhundred microns in thickness and are connected electrically in series toform strings. Multiple strings are further connected in series or inparallel, arranged on a supporting glass pane, and encapsulated withpolymeric resin and film to form a photovoltaic module. The module isusually provided with a frame to form the photovoltaic panel.

A second generation photovoltaic panel involves utilizing a thin-film ofsemiconductor material, for example hydrogenated amorphous silicon(a-Si:H), as the active photovoltaic material. The a-Si:H film isdeposited on a supporting superstrate in a glow discharge of silane gas.Resulting thin-film silicon devices exhibit solar conversionefficiencies in excess of ten percent (10%). A unit cell and the tandemcell or multi-junction amorphous silicon solar cell can only provide asmall output voltage of up to a few volts (a single junction ˜0.9 V;tandem junction ˜1.6V; multi-junction, depending upon the number ofjunctions, more than 2 V). So, a number of solar cells are typicallyelectrically interconnected in series to produce working voltages.

When all cells in an array are illuminated, each cell will be forwardbiased. However, if one or more of the cells is partially shaded orshadowed (i.e., not illuminated), such as by falling leaves, snow, or ifthere are physical differences in the cells such as caused by cellbreakage, this mismatch in the properties of interconnected cells cancreate operating problems for series connected solar cells. Thismismatch of different cell in output can dramatically decrease theoutput current of the entire module, and in some cases the mismatchedunit cell merely functions as a load to cause heat generation or reversebias. The excess heat or the strong reverse bias voltage may permanentlydamage the unit cell or possibly melt the encapsulate material.

To guard against such damage it is known to provide a protective bypassdiode. One bypass diode may be connected across several cells, or, forenhanced reliability, each cell may have its own bypass diode connectedin parallel and in an opposite direction thereto, thereby reducing theinfluence of such a mismatch. If the cells are working normally withfully illumination and producing energy, the bypass diodes are reversebiased and the current flow is through the cells. However, if anymismatch happens, the current flow through the cell becomes limited andreverse biased, the parallel-connected bypass diode becomes forwardbiased, and current flow is conducted through the bypass diode, therebyprotecting the affected cell.

U.S. Pat. Pub. No. 2002/0164,834 (Boutros et al.) discloses a method formaking a solar cell with an integrated bypass diode. The methodcomprises multiple steps of depositing layers with opposite type anddifferent level of dopants on one surface layer of the solar cell toform a bypass diode.

U.S. Pat. No. 6,784,358 (Kukulka) shows a solar cell structure with adiscrete amorphous silicon bypass diode. A discrete amorphous siliconbypass diode is supported on either the first or second metallizationlayer of the cell.

The above mentioned configurations, however, require additionalsemiconductor steps to incorporate the diode into the substrate. Theapproaches are complex and cause assembly difficulties, for example inthe case of series connections, it is very complicated. Manufacturingcost increase commensurately.

Accordingly, in view of the foregoing, it is believed advantageous toprovide an efficient method for production of photovoltaic panels withcell-level integrated bypass diodes with reduced costs.

SUMMARY OF THE INVENTION

In general, the present invention relates to a method for manufacturinga thin-film silicon photovoltaic cell having a cell level integratedbypass diode and to the photovoltaic cell produced thereby.

The method includes the formation of an array of series-connected solarcells on a support layer. The array includes at least a first, a secondand a third solar cell. Each solar cell is a laminated structurecomprising: a photovoltaic junction layer including a semiconductingmaterial of a first type and a semiconducting material of a second type;a front electrode disposed in electrical contact with the semiconductingmaterial of the first type; and a back electrode disposed in electricalcontact with the semiconducting material of the second type.

In accordance with the present invention the method also includes thesteps of:

-   -   separating from a selected parent solar cell at least a portion        of both the back electrode and the photovoltaic junction layer;        and    -   using the separated portion of the back electrode, connecting        the semiconducting material of the second type of the separated        portion of the photovoltaic junction layer to the semiconducting        material of the first type of any one chosen solar cell in the        array.

The semiconducting material of the first type in the separatedphotovoltaic portion of the junction layer may be connected to eitherthe same or a different chosen solar cell in the array such that abypass diode is disposed parallel with and in opposition to one or morecells in the array.

In one embodiment of the invention, during the separating step, thefront electrode of the parent solar cell is left intact so that thesemiconducting material of the first type of the separated portion ofthe photovoltaic junction layer is electrically connected with thesemiconducting material of the second type of the second solar cellthrough physical contact between the front electrode of the first solarcell and the back electrode of the second solar cell.

In one instance of this embodiment, if the first and second solar cellsare adjacent to each other, during the connecting step thesemiconducting material of the second type of the separated portion ofthe photovoltaic junction layer is connected with the semiconductingmaterial of the first type of the second solar cell so that a bypassdiode that is connected in parallel with and in opposition to the secondsolar cell is defined.

In another instance of this embodiment, if the first, second and thirdsolar cells are adjacent to each other, during the connecting step thesemiconducting material of the second type of the separated portion ofthe photovoltaic junction layer is connected with the semiconductingmaterial of the first type of the third solar cell, the bypass diodebeing connected in parallel and in opposition to both the second andthird solar cells.

In yet another instance of this embodiment, if the first and second areadjacent and the third solar cell is spaced a predetermined number ofsolar cells away from the second solar cell, the semiconducting materialof the second type of the separated portion of the photovoltaic junctionlayer may be connected with the semiconducting material of the firsttype of the third solar cell, so that the bypass diode is connected inparallel and in opposition to the second and third solar cells and toall solar cells therebetween.

In an alternate embodiment of the invention, during the separating stepa portion of the front electrode is also separated from the parent solarcell thereby totally segregating the separated portions of the frontelectrode, back electrode and photovoltaic junction layer from the firstsolar cell.

The semiconducting material of the second type of the separated portionof the photovoltaic junction layer may be connected with thesemiconducting material of the first type of either the parent solarcell or of any other chosen cell. The semiconducting material of thefirst type of the separated portion of the photovoltaic junction layermay also be connected to the semiconducting material of the second typeof either the parent cell or the same or a different chosen cell.

For example, if the first and the second solar cells are adjacent toeach other, and if the first solar cell is the parent solar cell, thesemiconducting material of the second type of the separated portion ofthe photovoltaic junction layer may be connected with the semiconductingmaterial of the first type of either the parent solar cell or the secondsolar cell. The semiconducting material of the first type of theseparated portion of the photovoltaic junction layer may be connected tothe semiconducting material of the second type of either the parent cellor the second solar cell. If the materials of the junction layer areeach connected to the respective opposite polarity materials of the samecell (i.e., both to either the parent or to the second cell), then thebypass diode is connected in parallel and in opposition to that cell.

If the materials of the junction layer are connected to the oppositematerials different cells (i.e., to the parent and to the second cell),then the bypass diode is connected in parallel and in opposition tothose cells.

In the cell array produced as a result of the method of the presentinvention the bypass diode is spaced from the selected parent solar cellalong the axis of the parent solar cell. In addition, in the preferredinstance, corresponding interfaces between each semiconducting materialand the electrode with which it is in contact in both the parent solarcell and in the bypass diode are substantially coplanar with therespective first and second interfaces defined in the parent solar cell.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more fully understood from the following detaileddescription taken in connection with the accompanying drawings, whichform a part of this application, and in which:

FIGS. 1A, 1B and 1C are diagrammatic, front elevation views entirely insection illustrating the structures formed in an array of photovoltaicsolar cells after each of a series of process steps in accordance withone common prior art manufacturing process, while FIG. 1D is a plan viewof the array of cells shown in FIG. 1C, and FIG. 1E is the equivalentcircuit diagram of the finished cell array;

FIG. 2A is a plan view illustrating the array of cells shown in FIGS. 1Cand 1D wherein an etchant is disposed in a predetermined pattern inaccordance with the present invention;

FIG. 2B is an elevation view, in section, taken along section lines2B-2B in FIG. 2A;

FIG. 3A is a stylized perspective view illustrating the structure of twoadjacent cells and adjacent bypass diodes resulting after removal of theetchant, with one of the bypass diodes being connected in parallelopposition to one of the cells;

FIG. 3B is an equivalent circuit diagram of the cell with opposed bypassdiode arrangement shown in FIG. 3A;

FIG. 4A is a plan view generally similar to FIG. 2A illustrating thearray of cells shown in FIGS. 1C and 1D wherein an etchant is disposedin an alternative predetermined pattern in accordance with the presentinvention;

FIG. 4B is a stylized perspective view generally similar to FIG. 3Aillustrating the structure of four adjacent cells and adjacent bypassdiodes resulting after removal of the etchant disposed in accordancewith the pattern of FIG. 4A, in which one bypass diode is associatedwith and able to provide bypass protection for more than one solar cell;

FIG. 4C is an equivalent circuit diagram of the modified arrangementshown in FIG. 4B;

FIG. 5 is a stylized perspective view illustrating the structure of twoadjacent cells and adjacent bypass diodes resulting after removal of thefirst etching paste according to a first implementation of the secondembodiment of the present invention;

FIG. 6A is a plan view illustrating the array of cells shown in FIG. 5wherein a second etching paste is disposed in a second predeterminedpattern according to the implementation of the second embodiment of thepresent invention useful when the front electrode is fabricated from anetchant-resistant material;

FIG. 6B a stylized perspective view illustrating the structure of twoadjacent cells and two totally separated adjacent bypass diodesresulting after removal of the second etching paste, with the bypassdiode being connected to the corresponding cell according to the secondembodiment of the present invention;

FIG. 6C is an equivalent circuit diagram of the cell with the bypassdiode being connected to the corresponding cell shown in FIG. 6Baccording to the second embodiment of the present invention;

FIG. 6D is a stylized perspective view, similar to FIG. 6B, illustratinga totally separated bypass diode connected to a chosen solar cell in thearray other than the parent solar cell;

FIG. 6E is an equivalent circuit diagram of the cell with the bypassdiode being connected as shown in FIG. 6D;

FIG. 6F is a stylized perspective view, similar to FIG. 6B, illustratingthe structure of two adjacent cells and a single bypass diode, with thebypass diode being connected to the corresponding parent cell and atleast one additional cell according to the first implementation of thesecond embodiment of the present invention;

FIG. 6G is an equivalent circuit diagram of the cell with the bypassdiode being connected as shown in FIG. 6F;

FIG. 6H is a stylized perspective view, similar to FIG. 6F, illustratingthe structure of three adjacent cells and a single bypass diode, withthe bypass diode being connected to the its parent cell and at least oneadditional cell, with at least one intermediate cell being disposedtherebetween;

FIG. 6I is an equivalent circuit diagram of the cell with the bypassdiode being connected as shown in FIG. 6H;

FIG. 7A is a plan view, similar to FIG. 6A, showing the disposition ofan etching paste according to an alternate implementation of the secondembodiment of the present invention useful when the front electrode isfabricated from an etchant-susceptible material;

FIG. 7B is a stylized perspective view illustrating a totally separated,dual-lobed bypass diode produced as a result of the etching pastedisposed as in FIG. 7A.

DETAILED DESCRIPTION OF THE INVENTION

Throughout the following detailed description similar reference numeralsrefer to similar elements in all Figures of the drawings. It should beunderstood that details illustrating the structure of the presentinvention as shown in various Figures have been stylized in form, withsome portions enlarged or exaggerated, all for convenience ofillustration and ease of understanding.

FIGS. 1A through 3B collectively illustrate the various steps in amethod in accordance with a first embodiment of present invention forproducing a thin-film photovoltaic solar cell with an associated celllevel integrated bypass diode. The term “cell level” as used in thisapplication means that each bypass diode is produced from the structureof a parent solar cell and the diode is associated with and able toprovide bypass protection for at least one photovoltaic solar cell.

However, it should be understood that a bypass diode formed inaccordance with this embodiment of the present invention may beassociated with and provide bypass protection for more than one cell, ifdesired. An illustration of a modified step in the method and thestructure and corresponding circuit diagram of the resultant cell/bypassdiode combination are shown in FIGS. 4A, 4B and 4C.

The first step in the method comprises forming an array generallyindicated by the reference character 40 (e.g., FIGS. 1C, 1D) thatincludes at least two or more photovoltaic solar cells on the interiorsurface 121 of a support layer 12. The support layer 12 has an exteriorsurface 12E. The support layer 12 can take any convenient shape but itis usually rectangular (or square) in plan (as illustrated herein). Ifthe surface 12E eventually defines the sun-facing top surface of afinished photovoltaic panel the support layer is usually termed a“superstrate” and is made of a etchant-resistant transparent material,typically glass or a polymer. Since in the embodiments being describedthe support layer does define the sun-facing surface of the array beingformed, the term “superstrate” shall be used hereafter. However, itshould be understood that the present invention is also applicable to anarrangement in which the support layer does not face the sun. In thisinstance the support layer is usually termed a “substrate”. Thesubstrate may be made of etchant-resistant glass, polymer or anon-transparent metal. Although one preferred method of realizing thearray of solar cells is described in detail herein, it should beappreciated that the array may be realized using any desired fabricationmethod.

FIGS. 1A through 1C are diagrammatic front elevation views entirely insection across the width dimension of a portion of the array 40 ofseries-connected photovoltaic solar cells formed on the superstrate 12.FIGS. 1A through 1C illustrate the structures of the solar cellsproduced after each of a series of process steps in accordance with onecommon prior art manufacturing process substantially as disclosed inU.S. Pat. No. 4,292,092 (Hanak). FIG. 1D is a plan view of a portion ofthe lengthwise dimension of the cell array 40 shown in FIG. 1C, whileFIG. 1E is a circuit diagram of the portion of the array 40 shown inFIGS. 1C and 1D. The portion of the array 40 illustrated in FIGS. 1C and1D contains five adjacent photovoltaic solar cells, respectivelyindicated by reference characters 40A, 40B, 40C, 40D and 40E, althoughit should be understood that any convenient number of cells greater thantwo may be fabricated. In a typical instance, a support layer measuringthree-by-five (3×5) feet could contain an array having N solar cells,where N may be on the order of one hundred (100) solar cells, with eachcell being approximately 0.35 inches in width.

FIG. 1A shows an early step in the formation of the array 40. In thisstep substantially the entire interior surface 121 of the superstrate 12is coated with a layer of a transparent conducting oxide (TOO),generally indicated by the reference character 16. The TCO layer usuallyhas a thickness on the order of about one micrometer (1 μm). In thestructure discussed in FIGS. 1A through 3B the transparent conductiveoxide is an etchant-resistant electrode material. A suitableetchant-resistant TCO electrode material is halogen-doped tin oxide,such as fluorine-doped tin oxide (FTO). In a second embodiment of theinvention to be described the TCO electrode material may be anetchant-resistant material or a material susceptible to either an acidor basic etchant, such as indium doped tin oxide (ITO), zinc oxide(ZnO), gallium oxide (GaO) or tin oxide.

As shown in FIG. 1A the electrode layer 16 has a series of breaks 18formed therein. The breaks 18 extend through the full thickness of thematerial of the electrode layer 16 to the surface 121 of the glasssuperstrate 12. The breaks 18 subdivide the electrode layer 16 into aplurality of electrically isolated strips 16A through 16E. Each strip16A through 16E extends lengthwise along the superstrate 12 (i.e., intothe plane of FIGS. 1A,1C and along the plane of FIG. 1D). Each strip 16Athrough 16E serves to define an incident, or front, electrode for arespective solar cell 40A through 40E, as will be described.

The breaks 18 may be formed using a laser-scribing process. Laserscribing involves scanning a focused laser beam of sufficient power andappropriate wavelength to ablate a narrow width of the electrode layeralong the scan line.

Since the electrode material is etchant-resistant it is difficult toremove chemically. Accordingly, before or after the laser scribing thatproduces the breaks 18 the entire peripheral margin of the electrodelayer 16 is removed by mechanical action, such as grinding or sandblasting. A portion of the removed region 16R of the electrode layer 16is indicated in phantom lines on FIG. 1A. Removal of the region 16R fromthe margin of the electrode layer 16 exposes a portion of the interiorsurface 121 of the superstrate 12 and defines a peripheral edge 16Galong the width and/or length dimensions of the electrode strips. Theedge 16G is typically located at about one centimeter (1 cm) inwardly ofthe peripheral edge 12P of the superstrate 12. Since such mechanicalremoval is a dusty process it is usually performed away from the cleanroom area where the other steps of the process are performed. Aftermechanical removal of the electrode material the superstrate 12 isthoroughly washed in preparation for further processing steps.

As a next step, illustrated in FIG. 1B, a photovoltaic junction layergenerally indicated by the reference character 22 is deposited over thesuperstrate 12 and the electrode strips 16A through 16E thereon. Inpractice, the junction layer 22 is the active region of the solar cell(and any diode formed therefrom) and comprises at least one stratum of asemiconducting material of a first type (e.g., “p-type” amorphoussilicon material), at least one stratum of a semiconducting material ofa second type (e.g., “n-type” amorphous silicon material), and,optionally, one or more intermediate stratum(a) of an intrinsicsemiconducting material. In the drawings the strata of “p-type” and the“n-type” amorphous semiconducting materials in the junction layer 22 areillustrated by hatching and any intermediate stratum(a) of intrinsicsemiconducting material is indicated by stippling. As seen in FIG. 1Bthe junction layer 22 extends into and fills the breaks 18 betweenadjacent front electrode strips. The junction layer 22 extends beyondthe edge 16G of the electrode 16A and lies directly on the exposed glassextending along the peripheral regions of the superstrate 12. Theabsence of electrode material in these peripheral regions imparts arolled-off contour 22R to the junction layer 22 along the portions ofthe perimeter of the superstrate 12 from which the front electrode isremoved. It should be noted that if bypass diodes are to be formed inaccordance with either implementation of the second embodiment of theinvention (to be discussed herein), the removal of electrode materialfrom the region 16R along the peripheral margin of the array may beomitted.

Each of the various strata of materials forming the photovoltaicjunction layer may be deposited using any one of a variety of depositiontechniques, including PECVD, hot wire CVD, and photochemical vapordeposition in the presence of silane and other alloying and dopinggases, for example phosphine for n-type amorphous silicon and diboranefor p-type amorphous silicon. Typically each silicon stratum ranges inthickness from a few hundred nanometers (amorphous silicon) to a fewthousand nanometers (microcrystalline silicon), such that the overallthickness of the junction layer is on the order of few hundrednanometers to a few micrometers. The strata of “p-type” and the “n-type”materials may be reversed in a “substrate” structure which can usenon-transparent material as the support layer and in which light entersfrom the opposite side of the cell.

Once deposited, the photovoltaic layer 22 is itself separated intoadjacent strips 22A through 22E of semiconducting material by breaks 26.The breaks 26 may be formed by laser scribing. The breaks 26 runparallel to but slightly displaced from the breaks 18 between adjacentfront electrode strips. Each break 26 extends through the full thicknessof the junction layer 22 and exposes a portion of the surface of a frontelectrode strip 16A through 16E, as the case may be.

The next step in the process of forming the array 40 of photovoltaicsolar cells is shown in FIGS. 1C and 1D. In this step a second layer ofan electrically conductive material, generally indicated by thereference character 28, is deposited over the entire photovoltaicjunction layer 22. This second conductive layer 28 forms the backelectrode of each solar cell in the array.

The conductive material of the second conducting layer 28 not onlycovers the entire surface of each strip 22A through 22E of the junctionlayer, but also extends into and fills the breaks 26 to make electricalcontact with the surface of the front electrode strip exposed by thebreak 26. The contact point between paired back and front electrodes isindicated in the Figures by reference character 30. The back electrodelayer 28 also exhibits a rolled-off contour 28R imparted due to presenceof the rolled contour 22R of the photovoltaic layer 22 defined along theperiphery of the superstrate 12.

The material of the back electrode 28, for example, silver, may bedeposited by sputtering to a thickness on the order of a few hundrednanometers. Of course, a different conductive material may be used andapplied in any convenient manner. For example, for some siliconthin-film modules, in order to improve electrical performance the backelectrode may be formed from two or more layers of chemically distinctmaterials. Such a dual layer back electrode comprising a first stratumof zinc oxide (ZnO) and a second stratum of silver is well known.

A third laser scribing operation forms breaks 32 that run parallel tobut slightly displaced from the breaks 26 in the junction layer 22. Thebreaks 32 separate the second electrode layer 28 into adjacent strips28A through 28E. Usually the breaks 32 also extend through therespective strips 22A through 22E of the photovoltaic junction layerlying beneath the electrode strips 28A through 28E.

The regions 34B are electrically short-circuited “dead regions” becausethe front side electrode (FTO) and back side electrode (metal) areconnected.

As described in U.S. Pat. No. 4,292,092 (Hanak), a continuously excited(CW) neodymium YAG laser radiating at 1.06 micrometers operated in aQ-switched mode at a pulse rate of about 36 kHz and a scribing rate ofabout 20 cm/sec can be used in the laser scribing process. The power forfirst laser scribe (breaks 18 in the TCO layer) is about 4.5 watts. Thepower for the laser scribe to form the breaks 26 (FIG. 1B, TCO+a-Si) isabout 1.7 watts, and the power for the laser scribe to form the breaks32 (FIG. 1C, a-Si+metal) is about 1.3 watts.

The net result of the combination of steps shown in FIGS. 1A through 1Dis the formation of an array 40 comprising a plurality of individualphotovoltaic solar cells 40A through 40E each supported on thesuperstrate 12. Each solar cell 40A through 40E has a respective majoraxis 41A through 41E (FIGS. 1D, 2A, 3A) that extends along thelengthwise dimension of the array. Each solar cell 40A through 40E isformed as a laminated structure comprising:

-   -   a photovoltaic junction layer (22A through 22E, respectively)        having at least a semiconducting material of a first type and a        semiconducting material of a second type;    -   a respective front electrode 16A through 16E (in this embodiment        formed of an etchant-resistant transparent conductive oxide);        and    -   a respective back electrode 28A through 28E.

Each front electrode 16A through 16E is in electrical contact with onestratum of semiconducting material in a respective strip 22A through 22Eof the junction layer. The interface 36A through 36E between a frontelectrode 16A through 16E and one of the semiconducting materials of itsassociated junction layer strip 22A through 22E is indicated in theFigures as a bold dark line. The major portion of each interface 36Athrough 36E (other than the rolled-off contour 28R of the cell 40A) issubstantially planar and extends substantially parallel to the interiorsurface 121 of the superstrate 12.

Each back electrode 28A through 28E is in electrical contact with onestratum of semiconducting material in its respective associated strip22A through 22E of the junction layer. The major portion of theinterface 38A through 38E between a back electrode 28A through 28E andone of the semiconducting materials of its associated junction layerstrip 22A through 22E (again excluding consideration of the rolled-offcontour 28R of the cell 40A) appear as a bold dark line in the Figures.The major portion of each interface 38A through 38E is alsosubstantially planar and extends substantially parallel to the interiorsurface 121 of the superstrate 12.

An equivalent electrical schematic diagram of the diode array isillustrated in FIG. 1E. Each diode in the array is electricallyconnected in series with an adjacent diode by virtue of the electricalcontact (for example, as illustrated at contact points 30B through 30Ein FIG. 1C) between the front electrode of one cell with the backelectrode of an adjacent cell.

In accordance with the first embodiment of the present invention a celllevel bypass diode for each solar cell is formed by separating orsegregating a relatively smaller sized portion of the laminatedstructure from a solar cell. Each separated portion 44A through 44E(FIG. 3A), when interconnected as will be discussed, defines the celllevel bypass diode for one or more adjacent cells.

Each bypass diode may be separated from a parent solar cell by theapplication of at least one selected chemical etchant material depositedin a predetermined “positive” pattern over the photovoltaic cell array40. This technique is described more fully herein.

Alternatively, a masking paste may be applied in an inverse patternwhich leaves the unmasked areas uncovered. After the masking paste isdried, the unmasked areas are exposed to a wet etchant. The unmaskedareas may be exposed by applying the wet etchant directly thereto or byimmersing the entire cell array into the wet etchant. The masking pasteis then stripped away. In this alternative method the pattern of themask is the invert of the “positive” pattern created when using etchantpaste.

A suitable masking paste typically comprises high-boiling solvents(boiling point>180° C.), such as terpineol(1-methyl-4-(1-methylvinyl)cyclohexan-1-ol) or texanol(2,2,4-trimethyl-1,3-pentanediolmono(2-methylpropanoate));acid-resistant polymers, such as co-polymers of methacrylic acid andmethyl methacrylate, polyphenols and epoxy resins; thermal orphotoinitiators; rheology modifiers, such as fumed silica or carbonblack; acid-resistant fillers, such as graphite, TiO₂, alumina, or tinoxide particles; pigment particles; surfactants; and optionally monomerscontaining two or more reactive groups. The masking paste is formulatedto provide good screen-printed fine features, long on-screen time, highetchant resistance, and ease of aqueous stripping. Masking pastecompositions can also be formulated to provide features such as goodenvironmental durability, good adhesion to the back electrode and panelencapsulant. They may be customized for color and texture.

FIGS. 2A and 2B show respective plan and cross sectional views of thearray 40 of FIGS. 1C and 1D with a coating of an etchant paste disposedover the back electrode surface in accordance with a first embodiment ofthe method of the present invention. The positive pattern of the etchantpaste is indicated in FIGS. 2A and 2B by the stippled hatching.

As best seen in FIG. 2A, to separate a bypass diode from each solar cellin the array the predetermined etchant paste pattern includes a stripe52 of paste that extends transversely across all of the solar cells 40Athrough 40E in a direction substantially perpendicular to the major axes41A through 41E of the cells. The stripe 52 is intersected by aplurality of relatively shorter stripes 54 of etchant paste that arepositioned as will be described between the major axes of adjacent cellsand extend generally parallel to those major axes. As suggested in FIG.4A, if it is not desired to separate a bypass diode from a given parentsolar cell, it is simply necessary to omit the portion of the stripe 52of etchant paste over that cell or cells.

The width dimension of the stripe 52 should be sufficient to separate ajunction layer of the diode being formed from its parent cell withoutunduly sacrificing operative surface area from that parent. A widthdimension on the order of about 0.2 cm is convenient to meet theseconflicting needs.

Each stripe 54 should be sufficiently wide and positioned so as tooverlie at least the location of the scribed break 18 in the frontelectrode layer 16. The width of each stripe 54 may optionally besufficient to cover the break 26 or both the breaks 26 and 32. FIGS. 2Aand 2B and FIG. 4A show the case in which the stripe 54 covers all threebreaks 18, 26 and 32 in the front electrode layer 16, the photovoltaicjunction layer 22, and the back electrode layer 28, respectively.

The etchant paste pattern may further include first and/or second edgeisolation stripe(s) 58, 60. The first edge isolation stripe(s) 58 (onlyone of which is illustrated in FIGS. 2A and 2B and 4A) extend(s) alongone or both of the lengthwise peripheral edges of the array 40.Additionally or alternatively, the second edge isolation stripe(s) 60(only one being illustrated in FIGS. 2A, 4A) extend(s) along one or bothof the widthwise peripheral edges of the array 40. The stripes 58 and/or60 should each have a width dimension on the order of about 0.6 cm whichis generally sufficient to produce edge isolation regions for furtherencapsulation of the cell array.

In general, the chemical composition of the etchant paste should beproperly formulated to provide effective etch removal of both the backelectrode layers and the junction layers lying within the predeterminedpaste pattern. The etchant paste may be either acidic or basic innature.

A suitable acidic etchant paste contains a silver and silicon etchantselected from the group consisting of nitric acid, hydrochloric acid,hydrofluoric acid, and mixtures thereof. A combination of nitric andhydrofluoric acids is preferred. The mixture of materials is carried ina polymer binder. Hydrochloric acid may be used to etch zinc oxide ormetals (such as aluminum) if such are used. Referencing the dual layerback electrode structure discussed earlier, hydrochloric acid can becombined with nitric acid to form an effective etchant paste for the ZnOand silver layers. The binder comprises polymeric materials selectedfrom the group consisting of poly(vinyl alcohol), poly(ethylene oxide),polyvinylpyrrolidone (PVP) poloxamers and mixtures thereof. Poloxamersare nonionic triblock copolymers composed of a central hydrophobic chainof polyoxypropylene, flanked by two hydrophilic chains ofpolyoxyethylene.

A suitable basic etchant paste contains multiple caustic etchingcomponents selected from the group consisting of alkali hydroxide (suchas sodium or potassium hydroxide), ammonium hydroxide andtetramethylammonium hydroxide. The basic mixture of materials is alsocarried in a polymer binder.

The etchant paste can be dispensed using any suitable dispensingtechnique used for screen, nozzle or ink-jet printing. This is a veryconvenient single step patterning technique requiring minimal equipment.

These same acids or bases can be used to produce a wet acidic etchantmaterial or a wet basic etchant material, as the case may be.

When using either an etchant paste or a wet chemical, the etchant pasteor a wet chemical is allowed to chemically etch the back electrode layerand the underlying junction layer for a predetermined dwell timedepending on the concentration of the etchant and the thickness of theback electrode and the silicon layer. For the thickness of the frontelectrode, photovoltaic and back electrode layers as discussed above, adwell time on the order of minutes is usually sufficient. As examples,for single junction a-Si cell, a dwell time on the order of one to twominutes may be sufficient. For a tandem junction solar cell whichincludes microcrystalline silicon (μc-Si), a more concentrated etchantis needed, otherwise a longer dwell time, on the order of five to tenminutes, is needed.

Optionally, in order to reduce the required dwell time, the chemicaletchant may be heated to a temperature in the range from about 50° C. toabout 200° C., and more particularly to a temperature in the range fromabout 50° C. to about 100° C. One convenient expedient for raising thetemperature of the chemical etchant is to raise the temperature of thesuperstrate using a suitable heating apparatus, such as a hot plate.

At the expiration of the dwell time the superstrate is sprayed with highpressure water or aqueous alkaline solution in order to wash off theetchant material. This insures no etchant material is present to causedeterioration of a resultant solar panel after encapsulation.

FIG. 3A shows a stylized perspective view of a portion of the arrayafter removal of the etchant paste. The paste is operative to removefrom each cell 40A, 40B selected portions of the back electrode and thephotovoltaic junction layer lying within the predetermined pattern (FIG.2A). Because the material of the front electrode is resistant to etchantit is exposed but left intact. The Si material in the scribed break 18between adjacent front electrode strips 16A, 16B is also removed. Thus,as a result of the etching action, each silicon solar cell strip whichhas been exposed to the etchant material is separated into two parts:viz., a major active cell (e.g., parent solar cells 40A, 40B) andrespective bypass diodes (e.g., diodes 44A, 44B).

Specifically, the bypass diode 44A includes both a portion 22′A of aphotovoltaic junction layer (separated from the photovoltaic junctionlayer 22A of the parent cell 40A) and a portion 28′A of the backelectrode (separated from the back electrode 28A of the parent cell 40A)(FIG. 3A). The primed reference characters indicate that the primedelements of the bypass diode were previously integral with thecorresponding elements of the solar cell. The separated portion of thejunction layer 22′A is supported by the front electrode 16A.

Structurally, the junction layer 22′A of the bypass diode 44A is spaceda predetermined distance 45 in a direction substantially parallel to themajor axis 41A from the junction layer 22A of the first cell 40A. Thispredetermined distance 45 is governed by the dimension of the stripe 52of etchant. Similarly, the lateral spacing between the adjacent bypassdiodes 44A, 44B is governed by the dimension of the etchant stripe 54.The dimensions of the stripes 52, 54 are selected such that the surfacearea of the bypass diode 44A is within the range from about one percent(1%) to about five percent (5%) of the surface area of the first solarcell 40A.

In addition to the axial spacing, in the preferred instance theinterface 36′A defined within the diode 44A between the front electrode16A and the one of the semiconducting strata of the separated junctionlayer 22′A is substantially coplanar with the corresponding interface36A defined in the parent cell 40A. Similarly, the interface 38′Adefined within the diode 44A between the back electrode 28′A and theother semiconducting strata of the separated junction layer 22′A issubstantially coplanar with the corresponding interface 38A in theparent cell 40A. However, it lies within the contemplation of thepresent invention that the interfaces 36A, 36′A may be vertically offsetwith respect to each other. Such a structural arrangement may beproduced, for example, by forming the superstrate 12 in such a way thatthe regions of the superstrate on which the bypass diodes will be formedare either relatively thicker or thinner than the thickness dimension ofthe regions of the superstrate on which the solar cells are formed.

The bypass diode 44B, separated by the action of the etchant from itsparent solar cell 40B, is analogously configured and supported on thefront electrode 16B.

It is noted that if edge isolation etchant stripe(s) 58 and/or 60 aredeployed the action of the etchant would remove both the back electrodeand the junction layers in those regions, thus exposing the peripheralmargins of the superstrate and define a set-back for the diodes 44A, 44Bfrom the widthwise edges of the superstrate.

The equivalent electrical schematic diagram of the interconnection ofthe diode 44A with the first and second solar cells 40A, 40B is shown inFIG. 3B. Electrically, the semiconducting material of the first type ofthe separated portion of the junction layer 22′A of the diode 44A isconnected via the front electrode 16A to the back electrode 28B, asillustrated by the dot-dash connection line 46. The front electrode 16Athus electrically links the semiconducting material of the first type ofthe separated portion of the junction layer 22′A with the semiconductingmaterial of the first type of the solar cell 40A and with thesemiconducting material of the second type of the second solar cell 40B(through the back electrode 28B of the second solar cell 40B).

A separate electrical connection 48 is defined between thesemiconducting material of the second type of the separated portion ofthe junction layer 22′A of the diode 44A and the semiconducting materialof the first type of the second solar cell 40B. Specifically, thisconnection 48 conveniently extends between the portion of the backelectrode 28′A of the diode 44A and the front electrode 16B of thesecond solar cell 40B.

The connection 48 may be implemented by a discrete wire to connect thebypass diode 44A with the front electrode 16B. Alternatively, ametallization may be printed using a screen, nozzle, or ink-jet printingtechnique to extend over the exposed peripheral portions of thesuperstrate. Disposing the metallization on the bare glass of the frontedge region of the superstrate avoids any shunt problem.

As a result of these electrical interconnections it may be appreciatedthat a cell level bypass diode (e.g., the diode 44A) may be formed onthe superstrate by separation from a parent solar cell and electricallyconnected in parallel and in opposition to a second solar cell (e.g.,the cell 40B). Each of the other bypass diodes separated from a cell inthe array may be interconnected with the adjacent cell in a manneranalogous to that described hereinabove. In such an arrangement eachdiode is connected in a one-to-one relationship with a solar cell.

Since the bypass diode 44A separated from the solar cell 40A has beeninterconnected with the adjacent cell 40B an external diode 62 isconnected by lines 63A, 63B between the respective front and backelectrode 16A, 28A of the cell 40A. The external diode 62 may beconveniently mounted on an edge isolation region of the superstrate. Theconducting lines 63A, 63B may be implemented by a metal paste dispensedon by screen, nozzle, or ink-jet printing techniques, or metal wiresapplied by soldering or any known methods.

Alternatively, the external diode 62 can be located in a completelyisolated area segregated from any part of the solar cell. Both the frontand back electrodes of this external diode 62 should be segregated frommain solar cells. To do so, for example, the front electrode can be cutby using laser scribing.

It should also be understood that the bypass diodes are photodiodes, andas such, generate current. But since the area of the bypass diode usedin the invention is so small compared to the active solar cells (forexample less than 5%, or more particularly about 1%), the diodes won'tinfluence the performance of the active solar cells.

The bypass diodes can also be optionally sheltered from illuminationwith an additional processing step that produces an opaque layer 64 onthe exterior surface 12E of the superstrate 12. An example of an opaquelayer 64 is indicated in FIG. 3A by dashed lines. As suggested in thedrawing the opaque layer 64 is positioned on the exterior surface 12E toalign with footprint of the diode 44A, thereby shadowing the same. Asuitable material for the opaque layer is dark paint or a polymer layerwith dark pigment.

As noted earlier it lies within the contemplation of the presentinvention that a diode needs not be separated from each solar cell inthe array 40. As shown in FIG. 4B diodes 44A, 44D have been separatedfrom their parent solar cells 40A, 40D. As a result of a positive orinverted paste pattern deployed as shown in FIG. 4A the cells 40B, 40Chave been left intact. Each solar cell (as cells 40B, 40C) from which adiode is not separated extends for their full length along thesuperstrate. However, a diode, such as the diode 44A that is formed byseparation from a parent solar cell 40A in accordance with the method ofthe present invention may be electrically connected in parallel and inopposition to additional cells beyond the next-adjacent (full length)solar cell 40B. For example, as shown in FIG. 4B the diode 44A may beconnected in parallel and opposition to a series connection thatincludes the next adjacent solar cell 40B and one (or more) spaced solarcells (e.g., the cells 40C, 40D or therebeyond).

These electrical connections and corresponding schematic diagram areillustrated in FIGS. 4B and 4C. The physical connection between theanode of the bypass diode 44A and the cathode of the next-adjacent solarcell 40B is effected through contact between the front electrode of thebypass diode 44A and the back electrode 28B of the next-adjacent solarcell 40B. The physical connection between the cathode of the bypassdiode 44A and the anode of another solar cell 40D is effected using aseparate electrical conductor 48′.

Still further, it should also be appreciated from the foregoing thatinstead of using an area of a solar cell disposed near an axial end, anarea of the solar cell intermediate the ends (e.g., a location near themiddle of the solar cell) can also be separated and used to form thebypass diode so long as a suitable modification to the paste pattern ismade. It is also within the contemplation of the invention to formseveral bypass diodes from a single cell. For example, the two end areasof the solar cell may be separated, and make two bypass diodes for asingle solar cell.

The array of thin film solar cells and bypass diode(s) formed asdescribed may be finished and formed into a photovoltaic panel byattaching a bus bar with solder and heat sealing with resin andfluoropolymer films, covering with an encapsulant adhesive 67 (such asEVA ethylene vinyl acetate copolymer) and a second exterior supportlayer 68.

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In accordance with a second embodiment of the present invention a celllevel bypass diode is formed by totally separating (or segregating) aportion of the complete laminated structure from one solar cell andappropriately interconnecting the separated portion to its parent and/orto one or more additional cells. As will be developed, in connectionwith this embodiment of the invention, the material used to form thefront electrode may be either an etchant-resistant material or anetchant-susceptible material. Depending upon the nature of the frontelectrode material the separation of a bypass diode from a parent cellmay be effected using one of two alternative implementation modes. In afirst implementation (FIGS. 5A, 6B) a bypass diode is separated from aparent cell using two discrete etching steps which sandwich anintermediate material conversion step. In an alternative implementation(FIG. 7A) the diode is formed using a single etching step.

The first step in practicing either implementation of the secondembodiment of the invention involves the disposition of a first etchingpaste in a first predetermined pattern over the back electrode surface.

The first predetermined etching paste pattern is the same as thatdescribed in the first embodiment shown in FIG. 2A. The pattern includesa first stripe 52 of the first etching paste that extends transverselyacross the first solar cell 40A in a direction substantiallyperpendicular to the major axis 41A of the first cell. The first stripe52 of the first etching paste is intersected by a plurality ofrelatively shorter stripes 54 that are positioned between the major axesof adjacent cells and extend generally parallel to those major axes.

The implementation of the second embodiment used when the frontelectrode is fabricated from an etchant-resistant material is discussedfirst. In this case the first etching paste used is the same as thatused in the first embodiment, comprising a first acidic etchant and abinder. The first acidic etchant contains only an etchant for thesemiconducting material and the back electrode. In general, the chemicalcomposition of the first acidic etchant should be properly formulated toprovide effective etch removal of both the back electrode layers and thejunction layers lying within the first predetermined etching pastepattern to expose the front electrode. The binder comprises polymericmaterials which is similar to those described in the first embodiment.

The first etching paste can be dispensed again using any suitabledispensing techniques such as used for screen, nozzle or ink-jetprinting.

The first etching paste pattern may further include first and/or secondedge isolation stripe(s) 58, 60 similar to those in the firstembodiment.

The first etching paste is allowed to chemically etch the back electrodelayer and the underlying junction layer for a first predetermined dwelltime depending on the concentration of the etchant and the thickness ofthe back electrode and the silicon layer. For the thickness of the backelectrode and photovoltaic layers as discussed above, a first dwell timeon the order of one to two minutes is usually sufficient.

Optionally, in order to reduce the required first dwell time, the firstchemical etching paste may be heated to a temperature in the range fromabout 50° C. to about 200° C., and more particularly to a temperature inthe range from about 50° C. to about 100° C. One convenient expedientfor raising the temperature of the first chemical etching paste is toraise the temperature of the superstrate using a suitable heatingapparatus, such as a hot plate.

At the expiration of the first dwell time the superstrate is sprayedwith high pressure water or aqueous alkaline in order to wash off thefirst etching paste.

It should be noted that a first etching paste that is basic in naturemay be used if the back electrode is fabricated from aluminum or from adual layer material of aluminum and zinc oxide.

FIG. 5 shows a stylized perspective view of the array after removal ofthe first etching paste. The first etching paste is operative to removefrom each cell 40A, 40B selected portions of the back electrode 28A, 28Band the photovoltaic junction layer 22A, 22B lying within the firstpredetermined pattern (FIG. 2A). Because the first etching paste isoperative only against the back electrode and the junction layers lyingwithin the first predetermined paste pattern, the front electrode 16A,16B is exposed but left intact. The scribed break 18 between adjacentfront electrode strips 16A, 16B is also exposed.

Since in this discussion it is assumed that the material forming thefront electrode is etchant-resistant, an intermediate materialconversion step is necessary to render the region of the front electrodeon which it is disposed susceptible to an etchant. A suitable conversionmaterial is zinc powder.

Once the conversion material is applied, a second etching material isdispensed in a second predetermined pattern over the now-convertedsurface zinc oxide surface of the front electrode.

FIG. 6A shows the second predetermined etching paste pattern asincluding a first stripe 82 of the second etching paste that extendstransversely across the first solar cell 40A in a directionsubstantially perpendicular to the major axis 41A of the first cell. Thefirst stripe 82 of the second etching paste is intersected by aplurality of a relatively shorter stripes 84 extends generally parallelto the major axes of adjacent cells.

The second predetermined etching paste pattern excludes an area adjacentto the parent solar cell and an area adjacent to the bypass diode thatdefine the outlines conductive tabs 90A, 94A projecting from the frontelectrode of the parent solar cell 40A and the bypass diode 44A. Thesetabs 90A, 94A are electrically connected to semiconducting material ofthe first type in the solar cell 40A and to the semiconducting materialof the first type in the bypass diode 44A. The tabs provide a convenientstructure whereby a bypass diode can be interconnected to one (or more)of the cells in the array. As shown, similar tabs are provided for theother cells and the bypass diodes separated therefrom.

The second etching paste pattern may further include first and/or secondedge isolation stripe(s) 58′, 60′ if they are included in the firstetching paste pattern.

A suitable second etching paste comprises a second acidic etchant and abinder. The second acidic etchant contains only an etchant for the frontelectrode. An example of the second acidic etchant for zinc oxide ishydrochloric acid. The second etching paste is dispensed over a portionof the exposed front electrode in the second predetermined pattern usingany suitable dispensing techniques such as those described in theapplication of the first etching paste. The binder in the second etchingpaste is the same as that in the first etching paste.

The second etching paste is allowed to chemically etch the frontelectrode layer for a second predetermined dwell time on the order ofone to two minutes depending on the concentration of the etchant and thethickness of the front electrode. Optionally, in order to reduce therequired second dwell time, the second chemical etching paste may beheated to a temperature in the range from about 50° C. to about 200° C.,and more particularly to a temperature in the range from about 50° C. toabout 100° C. Again one convenient expedient for raising the temperatureof the second etching paste is to raise the temperature of thesuperstrate using a suitable heating apparatus, such as a hot plate.

At the expiration of the second dwell time the superstrate is sprayedwith high pressure water or aqueous alkaline in order to wash off thesecond etching paste.

The second etching paste may alternatively be basic in nature.

Thus, as shown in FIG. 6B, as a result of the etching action eachsilicon solar cell stripe is separated into two parts: viz., a majoractive cell (e.g., parent solar cells 40A, 40B) with the conductive tab(e.g. 90A, 90B) and respective totally separated bypass diodes (e.g.,diodes 44A, 44B). Each totally separated bypass diode has a respectiveconductive tab (e.g. 94A, 94B), (FIG. 6B).

Specifically, the bypass diode 44A includes a portion 16′A of a frontelectrode layer (segregated from the front electrode layer 16A of theparent cell 40A), a portion 22′A of a photovoltaic junction layer(segregated from the photovoltaic junction layer 22A of the parent cell40A), and a portion 28′A of the back electrode (segregated from the backelectrode 28A of the parent cell 40A). It is stated for clarity that theprimed reference characters indicate that the primed elements of thebypass diode were previously integral with the corresponding elements ofthe solar cell but are now totally separated therefrom. The segregatedportion of the junction layer 22′A is supported by the front electrode16′A.

The interface 36′A defined within the diode 44A between the frontelectrode 16′A and the one of the semiconducting strata of thesegregated junction layer 22′A is substantially coplanar with thecorresponding interface 36A defined in the parent cell 40A. Similarly,the interface 38′A defined within the diode 44A between the backelectrode 28′A and the other semiconducting strata of the segregatedjunction layer 22′A is substantially coplanar with the correspondinginterface 38A in the parent cell 40A.

Structurally, the junction layer 22′A of the bypass diode 44A is spaceda predetermined distance 45 in the direction of the major axis 41A fromthe junction layer 22A of the first cell 40A. This predetermineddistance 45 is governed by the dimension of the stripe 52 of the firstetching paste. Similarly, the lateral spacing between the adjacentbypass diodes 44A, 44B is governed by the dimension of the etching pastestripe 54. The dimensions of the stripes 52, and 54 are selected suchthat the surface area of the bypass diode 44A is within the range fromabout 1% to about 5% of the surface area of the first solar cell 40A.

It is noted that if edge isolation etching paste stripe(s) 58 and/or 60are deployed the action of the first and the second etching paste wouldremove the back electrode, the junction layers, and the front electrodein those regions, thus obviating the need for the removal of material inthe region 16R as discussed in connection with the first embodiment.

The semiconducting material of the first type of the separated portionof the junction layer 22′A of the diode 44A is connected with thesemiconducting material of the second type of the parent solar cell 40Athrough the tab 94A of the front electrode of bypass diode 44A and theback electrode of the parent cell 40A by a conductor 96A. Thesemiconducting material of a first type of the solar cell 40A isconnected with the semiconducting material of the second type of thebypass diode (44A) through the tab 90A of front electrode of parent cell40A and the back electrode of bypass diode 44A by a conductor 98A. InFIG. 6B the conductors 96A, 98A (and 96B, 98B) are implemented usingmetal wire. The equivalent electrical schematic of the interconnectionof the diode 44A with the first solar cell 40A is shown in FIG. 6C.

Each of the other bypass diodes segregated from a cell in the array maybe interconnected with the corresponding parent cell in a manneranalogous to that described hereinabove.

Since the bypass diode is completely separated from its parent cell itis not necessary that the diode so formed be connected electricallyacross its parent. That is to say, a diode produced from any selectedparent cell may be connected in parallel with and in opposition to anycell (or cells) in the array.

For example, as shown in FIGS. 6D, 6E the diode 44A, totally separatedfrom its parent cell 40A, may be connected to the chosen cell 40B. Toeffect this connection the tab 94A projecting from the front electrode16′A of the diode 44A may be connected via the conductor 96A to the backelectrode 28B of the chosen cell 40B. The tab 90B projecting from thefront electrode 16B of the cell 40B is connected via the conductor 98Ato the back electrode 28′A of the diode 44A. FIG. 6E is the schematicdiagram of this connection.

The conducting lines 96A, 98A (96B, 98B, etc.) may be alternativelyimplemented by a metallization dispensed on by screen, nozzle, orink-jet printing techniques, or by a flexible circuit.

It should also be understood that the bypass diodes are photodiodes, andas such, generate current. But since the area of the bypass diode usedin the invention is so small compared to the active solar cells (<5%;for example, about 1%), the diodes won't influence the performance ofthe active solar cells.

The bypass diodes can also be optionally sheltered from illuminationwith an additional processing step that produces the opaque layer 64 onthe exterior surface 12E of the superstrate 12 (FIG. 6B).

The array of thin film solar cells and bypass diode(s) formed asdescribed may be finished into a photovoltaic panel by attaching a busbar with solder and heat sealing with resin and fluoropolymer films,covering with an encapsulant adhesive 67 (such as EVA ethylene vinylacetate copolymer) and a second exterior support layer 68 (broken awayfor clarity of illustration in FIG. 6B).

As alluded to earlier, a bypass diode 44A may be connected in parallelwith an opposition more than one cell in the array. FIGS. 6F and 6Gillustrate a situation in which a diode 44A is connected to provide abypass function for

one chosen cell, e.g., the parent cell 40A, and any other chosen cell,e.g., the cell 40B. In FIG. 6F the one chosen cell 40A and the otherchosen cell 40B are adjacent. (It is again noted that the parent cell ofthe diode 44A needs not be selected as the one chosen cell.) Theconnection is effected through a conductor 96A extending between the tab94A and the back electrode 28A of the one chosen cell and the conductor98A between the back electrode 28′A of the diode 44A and the tab 40B ofthe other chosen cell 40B.

FIGS. 6H and 6I illustrate an arrangement in which a single diode 44A isconnected across cells 40A, 40B, 40C. In this situation the one chosencell (the cell 40A) and the other chosen cell (in this case, the cell40C) are not adjacent.

Instead of using a second etching paste, it should be appreciated thatonce the front electrode has been exposed by the action of the first(acidic or basic) etching paste, the front electrode may be removedusing a laser.

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The implementation of the second embodiment utilized when the frontelectrode is fabricated from an etchant-susceptible material is nextdiscussed in connection with FIGS. 7A and 7B. A suitableetchant-susceptible material useful for the front electrode is selectedfrom the group consisting of: indium-tin oxide (ITO), zinc oxide (ZnO),gallium oxide (GaO) and tin oxide.

In this instance an etching paste operative against all of the layers ofthe laminate is dispensed in the desired pattern (e.g, the pattern asshown in FIG. 7A in which the diode to be formed overlies the secondscribe 26 and the third scribe 32). A suitable etching material for thispurpose may be either acidic or basic in nature (if the front electrodeis zinc oxide and the back electrode is either aluminum or a dual layeraluminum-zinc oxide).

As illustrated in FIG. 7B the etching material removes all the materialfrom the laminate and forms a bypass diode having two lobes 44A-1,44A-2. The lobes 44A-1, 44A-2 share the same front electrode.

The front electrode 16′A of the bypass diode is connected from the lobe44A-2 via the conductor 96A to the back electrode 28A of the solar cell40A. The back electrode 28′A of the lobe 44A-1 of the bypass diode isconnected via the conductor 98A to the front electrode 16A of the cell40A (through the back electrode 28B of the cell 40B. As in the case ofother connections, metal wires, flexible circuits or a metallization maybe used to implement the conductors 96A, 98A.

It should be appreciated that any of the etching steps outlined above inconnection with second embodiment may be alternatively implemented usingthe “inverse” techniques discussed earlier in connection with the firstembodiment. In these cases a masking paste may be applied in an inversepattern which leaves the unmasked areas uncovered. After the maskingpaste is dried, the unmasked areas are exposed to a wet etchant. Theunmasked areas may be exposed by applying the wet etchant directlythereto or by immersing the entire cell array into the wet etchant. Themasking paste is then stripped away. In this alternative method thepattern of the mask is the invert of the “positive” pattern created whenusing etchant paste. The masking paste mentioned earlier may be used.

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It should be apparent from the foregoing that in accordance with eitherembodiment of the present invention it is possible to utilize a smallamount of silicon thin-film solar cells (preferably along the end area),all solar cells in the panel are protected by the bypass diodes.

Those skilled in the art, having the benefit of the teachings of thepresent invention may impart modifications thereto. Such modificationsare to be construed as lying within the contemplation of the presentinvention, as defined by the appended claims.

1. A method for producing a thin-film solar cell with a cell levelintegrated bypass diode, the method comprising the steps of: a) formingan array of solar cells on a support layer, the solar cells beingconnected in electrical series, the array including at least a first, asecond and a third solar cell, at least the first and the second solarcells being adjacent to each other, the third solar cell being eitheradjacent to the second solar cell or separated by a predetermined numberof solar cells therefrom, each solar cell being a laminated structurecomprising: a photovoltaic junction layer having a semiconductingmaterial of a first type and a semiconducting material of a second type,a front electrode disposed in electrical contact with one of thesemiconducting materials, and a back electrode disposed in electricalcontact with the second one of the semiconducting materials, b)separating a portion of the photovoltaic junction layer from the firstsolar cell in the array; the semiconducting material of the first typeof the separated portion of the photovoltaic junction layer beingelectrically connected with the semiconducting material of the secondtype of the second solar cell through physical contact between the frontelectrode of the first solar cell and the back electrode of the secondsolar cell, c) connecting the semiconducting material of the second typeof the separated portion of the photovoltaic junction layer with thesemiconducting material of the first type of the third solar cell,whereby a bypass diode is defined on the first support layer, the bypassdiode being connected in parallel and in opposition to the second andthe third solar cells and all solar cells connected intermediatetherebetween.
 2. The method of claim 1 wherein the separating step b)itself comprises the steps of: b1) dispensing an etchant material in apredetermined pattern over the first solar cell, the etchant materialbeing able to etch through both the back electrode and the photovoltaicjunction layer of the portion of the first solar cell covered by theetchant.
 3. The method of claim 2 wherein the first solar cell has amajor axis therethrough, wherein the etchant material is an etchantpaste, and wherein the predetermined pattern includes a first stripeextending over the back electrode of the first cell in a directionsubstantially perpendicular to the major axis of the first cell, and asecond stripe intersecting the first stripe and extending over the backelectrode of the first cell in a direction substantially parallel to themajor axis of the first cell.
 4. The method of claim 3 wherein theetchant paste includes an acid selected from the group consisting ofnitric acid, hydrochloric acid, hydrofluoric acid, and mixtures thereof.5. The method of claim 3 wherein the etchant paste includes a baseselected from the group consisting of alkali hydroxide, ammoniumhydroxide and tetramethylammonium hydroxide and mixtures thereof.
 6. Themethod of claim 2 further comprising the step of: during step b),heating the etchant material to a temperature in the range from about50° C. to about 200° C.
 7. The method of claim 6 wherein the etchantmaterial is heated to a temperature in the range from about 50° C. toabout 100° C.
 8. The method of claim 1 further comprising the step of:d) covering the bypass diode with a protective layer able to shelter thebypass diode from illumination.
 9. The method of claim 1 wherein thefirst solar cell has a major axis therethrough, and wherein theseparating step b) itself comprises the steps of: b1) dispensing anmasking paste over a portion of the array thereby to define apredetermined unmasked pattern, wherein the predetermined unmaskedpattern includes: a first stripe extending over the back electrode ofthe first cell in a direction substantially perpendicular to the majoraxis of the first cell, and a second stripe intersecting the firststripe and extending over the back electrode of the first cell in adirection substantially parallel to the major axis of the first cell;b2) drying masking paste; b3) exposing the predetermined unmaskedpattern to a wet etchant, the wet etchant being able to etch throughboth the back electrode and the photovoltaic junction layer of theportion of the first solar cell within the unmasked pattern; and b4)removing the masking paste.
 10. The method of claim 9 wherein the wetetchant includes an acid selected from the group consisting of nitricacid, hydrochloric acid, hydrofluoric acid, and mixtures thereof. 11.The method of claim 9 wherein the wet etchant includes a base selectedfrom the group consisting of alkali hydroxide, ammonium hydroxide andtetramethylammonium hydroxide and mixtures thereof.
 12. The method ofclaim 1 further comprising the step of: d) connecting a second bypassdiode in parallel and in opposition to the first solar cell.
 13. Methodof making a solar panel comprising the steps of: a) providing a firstand a second support layer; b) forming an array of solar cells on asupport layer, the solar cells being connected in electrical series, thearray including at least a first, a second and a third solar cell, atleast the first and the second solar cells being adjacent to each other,the third solar cell being either adjacent to the second solar cell orseparated by a predetermined number of solar cells therefrom, each solarcell being a laminated structure comprising: a photovoltaic junctionlayer having a semiconducting material of a first type and asemiconducting material of a second type, a front electrode disposed inelectrical contact with one of the semiconducting materials, and a backelectrode disposed in electrical contact with the other one of thesemiconducting materials, c) forming a bypass diode on the first supportlayer by the steps of: i) separating a portion of the photovoltaicjunction layer from the first solar cell in the array; thesemiconducting material of the first type of the separated portion ofthe photovoltaic junction layer being electrically connected with thesemiconducting material of the second type of the second solar cellthrough physical contact between the front electrode of the first solarcell and the back electrode of the second solar cell, ii) connecting thesemiconducting material of the second type of the separated portion ofthe photovoltaic junction layer with the semiconducting material of thefirst type of the third solar cell in the array, whereby a bypass diodeis defined on the substrate, the bypass diode being connected inparallel and in opposition to the second and the third solar cells andall solar cells connected intermediate therebetween; and thereafter d)covering the array of solar cells and the bypass diode on the firstsupport layer with the second support layer.
 14. The method of claim 13wherein the first support layer comprises a transparent superstrate. 15.The method of claim 13 wherein the first support layer comprises anon-transparent substrate.
 16. The method of claim 13 wherein theseparating step c1) itself comprises the steps of: dispensing an etchantmaterial in a predetermined pattern over the first solar cell, theetchant material being able to etch through both the back electrode andthe photovoltaic junction layer of the portion of the first solar cellcovered by the etchant; and the method further comprising the step of:e) before step d), removing the etchant material from the first solarcell.
 17. The method of claim 16 wherein the first solar cell has amajor axis therethrough, wherein the etchant material is an etchantpaste, and wherein the predetermined pattern includes a first stripeextending over the back electrode of the first cell in a directionsubstantially perpendicular to the major axis of the first cell, and asecond stripe intersecting the first stripe and extending over the backelectrode of the first cell in a direction substantially parallel to themajor axis of the first cell.
 18. The method of claim 17 wherein theetchant paste includes an acid selected from the group consisting ofnitric acid, hydrochloric acid, hydrofluoric acid, and mixtures thereof.19. The method of claim 17 wherein the etchant paste includes a baseselected from the group consisting of alkali hydroxide, ammoniumhydroxide and tetramethylammonium hydroxide and mixtures thereof. 20.The method of claim 16 further comprising the step of: during step c),heating the etchant material to a temperature in the range from about50° C. to about 200° C.
 21. The method of claim 20 wherein the etchantmaterial is heated to a temperature in the range from about 50° C. toabout 100° C.
 22. The method of claim 13 further comprising the step of:e) covering the bypass diode with a protective layer able to shelter thebypass diode from illumination.
 23. The method of claim 13 wherein thefirst solar cell has a major axis therethrough, and wherein theseparating step c1) itself comprises the steps of: i) dispensing amasking paste over a portion of the array thereby to define apredetermined unmasked pattern, wherein the predetermined unmaskedpattern includes: a first stripe extending over the back electrode ofthe first cell in a direction substantially perpendicular to the majoraxis of the first cell, and a second stripe intersecting the firststripe and extending over the back electrode of the first cell in adirection substantially parallel to the major axis of the first cell;ii) drying masking paste; iii) exposing the predetermined unmaskedpattern to a wet etchant, the wet etchant being able to etch throughboth the back electrode and the photovoltaic junction layer of theportion of the first solar cell within the unmasked pattern; and iv)removing the masking paste.
 24. The method of claim 23 wherein the wetetchant includes an acid selected from the group consisting of nitricacid, hydrochloric acid, hydrofluoric acid, and mixtures thereof. 25.The method of claim 23 wherein the wet etchant includes a base selectedfrom the group consisting of alkali hydroxide, ammonium hydroxide andtetramethylammonium hydroxide and mixtures thereof.
 26. The method ofclaim 13 further comprising the step of: e) connecting a second bypassdiode in parallel and in opposition to the first solar cell.
 27. Amethod of making a solar panel comprising the steps of: a) providing afirst support layer having an array of solar cells connected inelectrical series on the first support layer, the array including atleast a first, a second and a third solar cell, at least the first andthe second solar cells being adjacent to each other, the third solarcell being either adjacent to the second solar cell or separated by apredetermined number of solar cells therefrom, each solar cell being alaminated structure comprising: a photovoltaic junction layer having asemiconducting material of a first type and a semiconducting material ofa second type, a front electrode disposed in electrical contact with oneof the semiconducting materials, and a back electrode disposed inelectrical contact with the other one of the semiconducting materials,the first support layer has a bypass diode formed by the steps of: i)separating from the first solar cell a portion of the photovoltaicjunction layer; the semiconducting material of the first type of theseparated portion of the photovoltaic junction layer being electricallyconnected with the semiconducting material of the second type of thesecond solar cell through physical contact between the front electrodeof the first solar cell and the back electrode of the second solar cell,ii) connecting the semiconducting material of the second type of theseparated portion of the photovoltaic junction layer with thesemiconducting material of the first type of the third solar cell,whereby a bypass diode is defined on the first support layer, the bypassdiode being connected in parallel and in opposition to the second solarcell and the third solar cells and all solar cells connectedintermediate therebetween; and thereafter b) covering the solar cellsand the bypass diode on the first support layer with a second supportlayer.